I was looking at the C standard extension (compressed instructions) section in the RISC-V ISA specification (Volume 1, Unprivileged Spec v. 20191213), and I realize that under a certain condition it is possible to increase the number of compact encodings. Here is how it can be done.
Take the second lowest bit of the program counter and call it the AOP bit. Then get the op field (the lowest two bit of the16-bit instruction field) and they form a pair. Now here is the new interpretation:
- If AOP bit is 0 (in other words, PC is divisible by 4), interpret the op field as before. We have the usual compressed instructions as before.
- If AOP bit is 1 (in other words, PC is not divisible by 4), we have two cases: if the op field is not 11, then we have the usual compressed instructions as before. But if the op field is 11, then we have a completely new space to create compressed instructions.
The disadvantage is that the new compressed instruction space can only appear in every other halfword in the instruction stream. But I think it could open up some possibilities, and decoding the AOP/op field should be only slightly more complicated.
I see one possible way is to support certain common instruction pairs, though I can't think of what pairs to encode though.
Thoughts? Post comments here!
